Communication among configurable logic circuits such as field programmable gate arrays (“FPGAs”) typically involves considerable host system involvement, which is highly undesirable and often unacceptable for supercomputing applications. For example, Xilinx FPGAs typically require host involvement in setting up registers for every data transfer.
In addition, supercomputing applications would be served advantageously by parallel involvement of multiple FPGAs capable of operating independently and without extensive host involvement.
Accordingly, a need remains for a system having both hardware and software co-design to provide for independent, direct and parallel communication among multiple configurable logic circuits such as a plurality of FPGAs. Such a system should further provide for minimal host involvement, and for significantly parallel and rapid data transfers, including to and from memory located anywhere within the system.